View ZL2101ALAF_8947204.PDF datasheet online --- IC-ON-LINE

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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. 6a digital synchronous step-down dc/dc converter with auto compensation zl2101 the zl2101 is a 6a digital converter with auto compensation and integrated power management that combines an integrated synchronous step-down dc/dc converter with key power management functions in a small pa ckage, resulting in a flexible and integrated solution. the zl2101 can provide an output voltage from 0.54v to 5.5v (with margin) from an input voltage between 4.5v and 14v. internal low r ds(on) synchronous power mosfets enable the zl2101 to deliver continuous loads up to 6a with high efficiency. an internal schottky bootstrap diode reduces discrete component count. the zl2101 al so supports phase spreading to reduce system input capacitance. power management features such as digital soft-start delay and ramp, sequencing, tracking, and ma rgining can be configured by simple pin-strapping or throug h an on-chip serial port. the zl2101 uses the pmbus? protoc ol for communication with a host controller and the digita l-dc bus for interoperability between other zilker labs devices. features ? integrated mosfet switches ? 6a continuous output current ? 1% output voltage accuracy ? auto compensation ? snapshot? parametric capture ?i 2 c/smbus interface, pmbus compatible ? internal non-volatile memory (nvm) applications ? telecom, networking, storage equipment ? test and measurement equipment ? industrial control equipment ? 5v and 12v distributed power systems related literature ? an2010 ?thermal and layout guidelines for digital-dc? products? ? an2033 ?zilker labs pmbus command set - ddc products? ? an2035 ?compensation using compzl?? figure 1. zl2101 efficiency 40 50 60 70 80 90 100 i out (a) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v in = 12v f sw = 200khz l = 6h v out = 3.3v january 23, 2012 fn7730.0 n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t p a r t z l 2 1 0 2
zl2101 2 fn7730.0 january 23, 2012 typical application circuit the following application circuit represents a typical implementation of the zl2101. fo r pmbus operation, it is recommended to tie the enable pin (en) to sgnd. block diagram v out 3.3v v in 12v i 2 c/ smbus ?? ddc bus ? enable c b 47nf c 25 10 f c dd 2.2 f c out 150 f l out 2.2h c in 100 f vset sa scl sda salrt fc pg sync dgnd zl2106 sw sw sw sw sw pgnd vddp sw bst vra vr vdds vddp vddp en v2 p5 mgn vsen sgnd pgnd pgnd pg nd pgnd cfg vtrk ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 e pad (sg nd) pgood c ra 4.7 f c r 4.7f ddc f.b. ? notes: ? ferrite bead is optional for input noise suppression. ? the ddc bus pull-up resistance will vary based on the capacitive loading of the bus , including the number of devices connected. the 10 k default value, assuming a maximum of 100 pf per device, provides the necessary 1 s pull-up rise time. please refer to the digital-dc bus section for more details. ?? the i 2 c/smbus pull -up resistance will vary based on the capacitive loading of the bus , including the number of devices connected. please refer to the i 2 c/smbus specifications for more details. figure 2. 12v to 3.3v/6a application circuit (5ms ss delay, 5ms ss ramp) zl2101 2.5v ldo pwm control & drivers sda scl sal rt vra v2 p5 vdds bst vsen vddp vset vtrk ss pg en cfg sw pgnd 7v ldo smbus sa nvm sync power mgmt ddc bus ddc v out mgn v in 5v ldo vr figure 3. block diagram
zl2101 3 fn7730.0 january 23, 2012 pin configuration zl2101 (36 ld qfn) top view vset sa scl sda salrt fc pg sync dgnd zl2106 sw sw sw sw sw pgnd vddp sw bst vra vr vdds vddp vddp en v2p5 mgn vsen sgnd pgnd pgnd pgnd pgnd cfg vtrk ss exposed paddle connect to sgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 ddc figure 4. zl2101 pin descriptions pin label type (note 1) description 1 pg o power-good. this pin transitions high 100ms after output voltage stabilizes within regulation band. selectable open drain or push-pull output. factory default is open drain. 2 dgnd pwr digital ground. common return for digital signals. connect to low impedance ground plane. 3synci/o, m (note 2) clock synchronization pin. used to set switching freq uency of internal clock or for synchronization to external frequency reference. 4 vset i, m output voltage select pin. used to set v out set-point and v out max. 5 sa i, m serial address select pin. used to assign unique smbus address to each ic. 6 scl i/o serial clock. connect to external host interface. 7 sda i/o serial data. connect to external host interface. 8 salrt o serial alert. connect to external host interface if desired. 9 fc i, m auto compensation configuration pin. used to set up auto compensation. 10 cfg i, m configuration pin. used to control the sync pin, sequencing and enable tracking. 11 ss i, m soft-start pin. used to set the ramp dela y and ramp time, sets uvlo and configure tracking. 12 vtrk i track sense pin. used to track an external voltage source. 13 vsen i output voltage positive feedback sensing pin. 14 sgnd pwr common return for analog signals. connect to low impedance ground plane. 15, 16, 17, 18, 19 pgnd pwr power ground. common return for internal switch ing mosfets. connect to low impedance ground plane. 20, 21, 22, 23, 24, 25 sw i/o switching node (level-shift common). 26 bst pwr bootstrap voltage for level-shift driver (referenced to sw). 27, 28, 29 vddp pwr bias supply voltage for internal switching mosfets (return is pgnd). 30 vdds pwr ic supply voltage (return is sgnd).
zl2101 4 fn7730.0 january 23, 2012 31 vr pwr regulated bias from internal 7v low-dropout regula tor (return is pgnd). decouple with a 4.7f capacitor to pgnd. 32 vra pwr regulated bias from internal 5v low-dropout regu lator for internal analog ci rcuitry (return is sgnd). decouple with a 4.7f capacitor to sgnd. 33 v2p5 pwr regulated bias from internal 2.5v low-dropout re gulator for internal digital circuitry (return is dgnd). decouple with a 10f capacitor. 34 ddc i/o digital-dc bus (open drain). interoperability between zilker labs devices. 35 mgn i margin pin. used to enable margining of the output voltage. 36 en i enable pin. used to enable the device (active high). epad sgnd pwr exposed thermal pad. common return for anal og signals. connect to low impedance ground plane. notes: 1. i = input, o = output, pwr = power or ground, m = multi-mode pins . please refer to section ?multi-mode pins? on page 11. 2. the sync pin can be used as a logic pin, a clock input or a clock output. pin descriptions (continued) pin label type (note 1) description ordering information part number (notes 4, 5) part marking temp range (c) package pkg. dwg. # ZL2101ALAF 2101 -40 to +85 36 ld 6mmx6mm qfn l36.6x6c ZL2101ALAFt (note 3) 2101 -40 to +85 36 ld 6mmx6mm qfn l36.6x6c ZL2101ALAFtk (note 3) 2101 -40 to +85 36 ld 6mmx6mm qfn l36.6x6c zl2101eval1z evaluation board notes: 3. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 4. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, wh ich is rohs compliant and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std -020. 5. for moisture sensitivity level (msl), please see device information page for zl2101 . for more information on msl please see techbrief tb363 .
zl2101 5 fn7730.0 january 23, 2012 table of contents absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 zl2101 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 digital-dc architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 power conversion overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 power management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 multi-mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin-strap settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 resistor settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 i2c/smbus method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power conversion functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 internal bias regulators and input supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 high-side driver boost circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 start-up procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 soft-start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power-good (pg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 configuration a: sync output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 configuration b: sync input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 configuration c: sync auto detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 design goal trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 bootstrap capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 cv2p5 selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 cvr selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 cvra selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 current sensing and current limit threshold selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 driver dead-time control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 power management functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 input undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output pre-bias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 voltage tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 tracking overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 tracking groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 tracking configured by pin-strap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 voltage margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 i2c/smbus communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 i2c/smbus device address selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 phase spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 monitoring via i2c/smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 snapshot? parametric capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 non-volatile memory and device security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
zl2101 6 fn7730.0 january 23, 2012 absolute maximum rating s thermal information dc supply voltage for vddp, vdds pins . . . . . . . . . . . . . . . . . . -0.3v to 17v high-side supply voltage for bst pin. . . . . . . . . . . . . . . . . . . . . -0.3v to 25v high-side boost voltage for bst - sw pins . . . . . . . . . . . . . . . . . -0.3v to 8v internal mosfet reference for vr pin . . . . . . . . . . . . . . . . . . -0.3v to 8.5v internal analog reference for vra pin . . . . . . . . . . . . . . . . . . -0.3v to 6.5v internal 2.5v reference for v2p5 pin . . . . . . . . . . . . . . . . . . . . . -0.3v to 3v logic i/o voltage for en, cfg, ddc, fc, mgn, pg, sda, scl, sa, salrt, ss, sync, vtrk, vset, vsen pins . . . . . . . . . . -0.3v to 6.5v ground differential for dgnd - sgnd, pgnd - sgnd pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v mosfet drive reference current for vr pin internal bias usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma switch node current for sw pin peak (sink or source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10a esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 2kv charged device model (tested per jesd22-c101d) . . . . . . . . . . . . 750v machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v latch-up (tested per jesd78c) thermal resistance (typical) ja (c/w) jc (c/w) 36 ld qfn (notes 6, 7) . . . . . . . . . . . . . . . . 28 1.7 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c dissipation limits (note 8) t a = +25c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5w t a = +55c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5w t a = +85c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4w pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions input supply voltage range, vddp, vdds (see figure 14) vdds tied to vr, vra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 5.5v vdds tied to vr, vra floating . . . . . . . . . . . . . . . . . . . . . . . . 5.5v to 7.5v vr, vra floating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5v to 14v output voltage range, v out (note 9) . . . . . . . . . . . . . . . . . . . . 0.54v to 5.5v operating junction temperature range, t j . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 8. thermal impedance depends on layout. 9. includes margin limits. electrical specifications v ddp = v dds = 12v, t a = -40c to +85c unless otherwise noted. (note 10) typical values are at t a = +25c. boldface limits apply over the operat ing temperature range, -40c to +85c. parameter conditions min (note 20) typ max (note 20) unit input and supply characteristics i dd supply current f sw = 200khz, no load - 11 20 ma f sw = 1mhz, no load - 15 30 ma i dds shutdown current en = 0v, no i 2 c/smbus activity - 0.6 1 ma vr reference output voltage v dd > 8v, i vr < 10ma 6.5 7.0 7.5 v vra reference output voltage v dd > 5.5v, i vra < 20ma 4.5 5.1 5.5 v v2p5 reference output voltage i v2p5 < 20ma 2.25 2.5 2.75 v output characteristics output current i rms , continuous - - 6 a output voltage adjustment range (note 11) v in > v out 0.6 - 5.0 v output voltage setpoint resolution set using resistors - 10 - mv set using i 2 c/smbus - 0.025 - % fs (note 12) vsen output voltage accuracy includes line, load, temp -1 - 1 % vsen input bias current vsen = 5.5v - 110 200 a soft-start delay duration range (note 13) set using ss pin or resistor 2 - 20 ms set using i 2 c/smbus 0.002 - 500 s
zl2101 7 fn7730.0 january 23, 2012 soft-start delay duration accuracy turn-on delay (precise mode) (notes 13, 14) - 0.25 - ms turn-on delay (normal mode) (note 15) - -0.25/+4 - ms turn-off delay (note 15) - -0.25/+4 - ms soft-start ramp duration range set using ss pin or resistor 2 - 20 ms set using i 2 c/smbus 0 - 200 ms soft-start ramp duration accuracy - 100 ? s logic input/output characteristics logic input leakage current digital pins -250 - 250 na logic input low, v il - - 0.8 v logic input open (n/c) multi-mode logic pins - 1.4 - v logic input high, v ih 2.0 - - v logic output low, v ol i ol 4ma - - 0.4 v logic output high, v oh i oh -2ma 2.25 - - v oscillator and switching characteristics switch node current, i sw peak (source or sink) (note 16) - - 9 a switching frequency range 200 - 1000 khz switching frequency set-point accuracy predefined settings (table 9) -5 - 5 % pwm duty cycle (max) factory default (note 17) - - 95 (note 18) % sync pulse width (min) 150 - - ns input clock frequency drift tolerance external clock source -13 - 13 % r ds(on) of high side n-channel fets i sw = 6a, v gs = 6.5v - 60 85 m r ds(on) of low side n-channel fets i sw = 6a, v gs = 12v - 43 65 m tracking vtrk input bias current vtrk = 5.5v - 110 200 a vtrk tracking ramp accuracy 100% tracking, v out - vtrk -100 - 100 mv vtrk regulation accuracy 100% tracking, v out - vtrk -1 - 1 % fault protection characteristics uvlo threshold range configurable via i 2 c/smbus 2.85 - 16 v uvlo set-point accuracy -150 - 150 mv uvlo hysteresis factory default - 3 - % configurable via i 2 c/smbus 0 - 100 % uvlo delay - - 2.5 s power-good v out threshold factory default - 90 - % v out power-good v out hysteresis factory default - 5 - % power-good delay using pin-strap or resistor 2 - 20 ms configurable via i 2 c/smbus 0 - 500 s electrical specifications v ddp = v dds = 12v, t a = -40c to +85c unless otherwise noted. (note 10) typical values are at t a = +25c. boldface limits apply over the operat ing temperature range, -40c to +85c. (continued) parameter conditions min (note 20) typ max (note 20) unit
zl2101 8 fn7730.0 january 23, 2012 vsen undervoltage threshold factory default - 85 - % v out configurable via i 2 c/smbus 0 - 110 % v out vsen overvoltage threshold factory default - 115 - % v out configurable via i 2 c/smbus 0 - 115 % v out vsen undervoltage hysteresis - 5 - % v out vsen undervoltage/overvoltage fault response time factory default - 16 - s configurable via i 2 c/smbus 5 - 60 s peak current limit threshold factory default - - 9.0 a configurable via i 2 c/smbus 0.2 - 9.0 a current limit set-point accuracy - 10 - % fs (note 12) current limit protection delay factory default - 5 - t sw (note 19) configurable via i 2 c/smbus 1 - 32 t sw (note 19) thermal protection threshold (junction temperature) factory default - 125 - c configurable via i 2 c/smbus -40 - 125 c thermal protection hysteresis - 15 - c notes: 10. refer to safe operating area in figure 8 and thermal design guidelines in an2010. 11. does not include margin limits. 12. percentage of full scale (fs) with temperature compensation applied. 13. the device requires a delay period following an enable sign al and prior to ramping its output. precise timing mode limits th is delay period to approximately 2ms, where in normal mode it may vary up to 4ms. 14. precise ramp timing mode is only valid when using en pin to enable the device rather than pmbus enable. precise ramp timing mode is automatically disabled for a self-enabled device (en pin tied high). 15. the devices may require up to a 4ms delay following the asse rtion of the enable signal (no rmal mode) or following the de-assertion of the enable signal. prec ise mode requires re-enable delay = t off +t fall +10s. 16. switch node current should not exceed i rms of 6a. 17. factory default is the initial value in firmware. the value can be changed via pmbus commands. 18. maximum duty cycle is limited by the equation max_duty(%) = [1 - (15010 -9 f sw )] 100 and not to exceed 95%. 19. t sw = 1/f sw , where f sw is the switching frequency. 20. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications v ddp = v dds = 12v, t a = -40c to +85c unless otherwise noted. (note 10) typical values are at t a = +25c. boldface limits apply over the operat ing temperature range, -40c to +85c. (continued) parameter conditions min (note 20) typ max (note 20) unit
zl2101 9 fn7730.0 january 23, 2012 typical performance curves for some applications, zl2101 operating conditions (input voltag e, output voltage, switching frequency, temperature) may requir e de-rating to remain within the safe operating area (soa). v in = v ddp = v dds , t j = +125c figure 5. low-side r ds(on) vs t j normalized for t j = +25c (v dds = 12v, i drain = 0.3a) figure 6. high-side r ds(on) vs t j normalized for t j = +25c (v dds = 12v, bst ? sw = 6.5v, i drain = 0.3a) figure 7. low-side r ds(on) vs v dds with t j figure 8. safe operating area, t j +125c figure 9. maximum conversion ratio, t j +125c 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0 255075100 t j (c) normalized r ds(on) 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0 255075100 t j (c) normalized r ds(on) 40 45 50 55 60 65 70 6 7 8 9 10 11 12 13 v dds (v) r ds(on) (m ) t j = +110c t j = +80c t j = +50c t j = +25c 0 1 2 3 4 5 6 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 1 2 4 5 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 f sw (mhz) v out (v) v in = 6v v in = 8.6v to 14v v in = 7.5v 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 f sw (mhz) v out /v in (v) v out may not exceed 5.5v at any time
zl2101 10 fn7730.0 january 23, 2012 zl2101 overview digital-dc architecture the zl2101 is an innovative mixed-signal power conversion and power management ic based on zilker labs patented digital-dc technology that provides an in tegrated, high performance step- down converter for point of load applications. the zl2101 integrates all necessary pwm control circuitry as well as low r ds(on) synchronous power mosfets to provide an extremely small solution for supplying load currents up to 6a. its unique pwm loop utilizes an ideal mix of analog and digital blocks to enable precise control of the entire power conversion process with no software required , resulting in a very flexible device that is also very easy to use. an extensive set of power management functions are fu lly integrated and can be configured using simple pin conn ections. the user configuration can be saved in an internal non-volatile memory (nvm). additionally, all functions can be configured and monitored via the smbus hardware interface using standard pmbus commands, allowing ultimate flexibility. once enabled, the zl2101 is immediately ready to regulate power and perform power management tasks with no programming required. advanced configuration options and real- time configuration change s are available via the i 2 c/smbus interface if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. integrated sub-re gulation circuitry enables single supply operation from any extern al supply between 4.5v and 14v with no secondary bias supplies needed. the zl2101 can also be configured to operate from a 3.3v or 5v standby supply when the main power rail is not present, allowing the user to configure and/or read diagnostic informat ion from the device when the main power has been interrupted or is disabled. the zl2101 can be configured by simply connecting its pins according to the tables provided in the following sections. additionally, a comprehensive set of application notes are available to help simplify the de sign process. an evaluation board is also available to help th e user become familiar with the device. this board can be evaluated as a standalone platform using pin configuration settings. a windows?-based gui is also provided to enable full configuration and monitoring capability via the i 2 c/smbus interface using an available computer and the included usb cable. power conversion overview the zl2101 operates as a voltage-mode, synchronous buck converter with a selectable constant frequency pulse width modulator (pwm) control scheme. th e zl2101 integrates dual low r ds(on) synchronous mosfets to minimize the circuit footprint. figure 10 illustrates the basic synchronous buck converter topology showing the primary power train components. this converter is also called a step-down converter, as the output voltage must always be lower than the input voltage. v in v out qh ql l 1 c out zl c in c b d b pw m ldo figure 10. synchronou s buck converter digital compensator input voltage bus v out bst digital compensator d-pwm + - vsen reset sync pll power management temp sensor mux en vset pg sa cfg vr sw vdd communication ref sync gen vtrk vdds scl sda salrt > > adc adc adc fc ldo vddp i sense hs fet driver ss vra i sense ddc mgn nvm ls fet driver digital compensator input voltage bus v out bst digital compensator d-pwm + - vsen reset sync pll power management temp sensor mux en vset pg sa cfg vr sw vdd communication ref sync gen vtrk vdds scl sda salrt > > adc adc adc fc ldo vddp i sense hs fet driver ss vra i sense ddc mgn nvm ls fet driver figure 11. zl2101 block diagram
zl2101 11 fn7730.0 january 23, 2012 the zl2101 integrates two n-channel power mosfets; qh is the top control mosfet and ql is the bottom synchronous mosfet. the amount of time that qh is on as a fraction of the total switching period is known as the duty cycle d , which is described by equation 1: during time d, qh is on and v in ? v out is applied across the inductor. the output current ramps up as shown in figure 12. when qh turns off (time 1-d), the current flowing in the inductor must continue to flow from the gr ound up through ql, during which the current ramps down. since the output capacitor c out exhibits low impedance at the switching frequency, the ac component of the inductor current is filtered from the output voltage so the load sees nearly a dc voltage. the maximum conversion ratio is shown in figure 9. typically, buck converters specify a maximum duty cycle that effectively limits the maximum output voltag e that can be realized for a given input voltage and switching frequency. this duty cycle limit ensures that the low-side mosfet is allowed to turn on for a minimum amount of time during each switching cycle, which enables the bootstrap capacitor to be charged up and provide adequate gate drive voltage for the high-side mosfet. in general, the size of components l 1 and c out as well as the overall efficiency of the circuit are inversely proportional to the switching frequency, f sw . therefore, the highest efficiency circuit may be realized by switching the mosfets at the lowest possible frequency; however, this will result in the largest component size. conversely, the smallest possible footprint may be realized by switching at the fastest possible frequency but this gives a somewhat lower efficiency. each user should determine the optimal combination of size and efficiency when determining the switching frequency for each application. the block diagram for the zl2101 is illustrated in figure 11. in this circuit, the target output voltage is regulated by connecting the vsen pin directly to the outp ut regulation point. the vsen signal is then compared to an in ternal reference voltage that had been set to the desired output voltage level by the user. the error signal derived from this comparison is converted to a digital value with an analog to digital (a /d) converter. the digital signal is also applied to an adjustable digital compensation filter and the compensated signal is used to derive the appropriate pwm duty cycle for driving the internal mosfets in a way that produces the desired output. power management overview the zl2101 incorporates a wide range of configurable power management features that are simple to implement without additional components. also, the zl 2101 includes circuit protection features that continuously safe guard the device and load from damage due to unexpected system faults. the zl2101 can continuously monitor input voltag e, output voltage/current and internal temperature. a power-good ou tput signal is also included to enable power-on reset functionality for an external processor. all power management functions ca n be configured using either pin configuration techniques (see figure 13) or via the i 2 c/smbus interface. monitoring parameters can also be pre- configured to provide alerts for specific conditions. see application note an2033 for more details on smbus monitoring. multi-mode pins in order to simplify circuit de sign, the zl2101 incorporates patented multi-mode pins that al low the user to easily configure many aspects of the device without programming. most power management features can be configured using these pins. the multi-mode pins can respond to four different connections, as shown in table 1. these pins are sampled when power is applied or by issuing a pmbus restore command (see application note an2033). pin-strap settings this is the simplest method, as no additional components are required. using this method, each pin can take on one of three possible states: low, open, or high. these pins can be connected to the v2p5 pin for lo gic high settings as this pin provides a regulated voltage high er than 2v. using a single pin one of three settings can be selected. in out v v d voltage (v) time current (a) v in -v out 0 -v out 1 - d i o il pk il v d figure 12. inductor waveform table 1. multi-mode pin configuration pin tied to value low (logic low) < 0.8vdc open (n/c) no connection high (logic high) > 2.0vdc resistor to sgnd set by resistor value zl multi-mode pin zl r set logic high logic low open pinstrap settings resistor settings multi-mode pin figure 13. pin-strap and resistor setting examples
zl2101 12 fn7730.0 january 23, 2012 resistor settings this method allows a greater range of adjustability when connecting a finite value resistor (in a specified range) between the multi-mode pin and sgnd. standard 1% resistor values are used, and only every fourth e96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. up to 31 unique selections are available using a single resistor. i 2 c/smbus method zl2101 functions can be configured via the i 2 c/smbus interface using standard pmbus commands. additionally, any value that has been configured using the pin-strap or resistor setting methods can also be re-configu red and/or verified via the i 2 c/smbus. see application no te an2033 for more details. the smbus device address and vout_max are the only parameters that must be set by external pins. all other device parameters can be set via the i 2 c/smbus. the device address is set using the sa pin. vout_max is determined as 10% greater than the voltage set by the vset pin. resistor pin-straps are recommended to be used for all available device parameters to allow a safe initial power-up before configuration is stored via the i 2 c/smbus. for example, this can be accomplished by pin-strapping the undervoltage lockout threshold (using ss pin) to a value greater than the expected input voltage, thus preventing the device from enabling prior to loading a configuration file. power conversion functional description internal bias regulators and input supply connections the zl2101 employs three internal low dropout (ldo) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. the in ternal bias regulators are as follows: ? vr: the vr ldo provides a regulated 7v bias supply for the high-side mosfet driver circuit. it is powered from the vdds pin and supplies bias current internally. a 4.7f filter capacitor is required at the vr pin. th e vdds pin directly supplies the low-side mosfet driver circuit. ? vra: the vra ldo provides a regulated 5v bias supply for the current sense circuit and other analog circuitry. it is powered from the vdds pin and supplie s bias current internally. a 4.7f filter capacitor is required at the vra pin. ? v2p5:the v2p5 ldo provides a regulated 2.5v bias supply for the main controller circuitry. it is powered from the vra ldo and supplies bias current internally. a 10f filter capacitor is required at the v2p5 pin. when the input supply (vdds) is higher than 7.5v, the vr and vra pins should not be connected to any other pins. these pins should only have a filter capaci tor attached. due to the dropout voltage associated with the vr and vra bias regulators, the vdds pin must be connected to these pins for designs operating from a supply below 7.5v. figure 14 illustrates the required connections for all cases. note: the internal bias regulators, vr and vra, are not designed to be outputs for powering other ci rcuitry. do not attach external loads to any of these pins. only the multi-mode pins may be connected to the v2p5 pin for logic high settings. high-side driver boost circuit the gate drive voltage for the high-side mosfet driver is generated by a floating bootstrap capacitor, c b (see figure 10). when the lower mosfet (ql) is turned on, the sw node is pulled to ground and the capacitor is ch arged from the internal vr bias regulator through diode d b . when ql turns off and the upper mosfet (qh) turns on, the sw node is pulled up to vddp and the voltage on the bootstrap capacito r is boosted approximately 6.5v above vddp to provide the necessary voltage to power the high- side driver. an internal schottky diode is used with c b to help maximize the high-side drive supply voltage. output voltag e selection the output voltage may be set to any voltage between 0.6v and 5.0v provided that the input volt age is higher th an the desired output voltage by an amount su fficient to prevent the device from exceeding its maximum duty cycle specification. using the pin-strap method, v out can be set to one of three standard voltages as shown in table 2. table 2. pin-strap output voltage settings vset v out low 1.2v open 1.5v high 3.3v 7.5v < v in 14v 4. 5v v in 5.5v 5.5v < v in 7.5v vr vra vdds v in vdds vr vra v in vdds vr vra v in figure 14. input supply connections
zl2101 13 fn7730.0 january 23, 2012 the resistor setting method can be used to set the output voltage to levels not available in table 2. to set v out using resistors, use table 4 to select the resistor that corresp onds to the desired voltage. the output voltage may also be set to any value between 0.6v and 5.0v using the i 2 c interface. see application note an2033 for details. start-up procedure the zl2101 follows a specific in ternal start-up procedure after power is applied to the vdd pins (vddp and vdds). table 3 describes the start-up sequence. if the device is to be synchronized to an external clock source, the clock frequency must be stable pr ior to asserting the en pin. the device requires approximately 5ms to 10ms to check for specific values stored in its internal memory. if the user has stored values in memory, those values will be loaded. the device will then check the status of all multi-mode pins and load the values associated with the pin settings. once this process is completed, the device is ready to accept commands via the i 2 c/smbus interface and the device is ready to be enabled. once enabled, th e device requires approximately 2ms before its output voltage may be allowed to start its ramp-up process. if a soft-start delay period less than 2ms has been configured (using pmbu s commands), the device will default to a 2ms delay period. if a delay period greater than 2ms is configured, the device will wait for the configured delay period prior to starting to ramp its output. after the delay period has expired, the output will begin to ramp towards its target voltage according to the pre-configured soft-start ramp time that has been set using the ss pin. it should be noted that if the en pin is ti ed to vddp or vdds, the device will still require approximately 5ms to 10ms before the output can begin its ramp-up as described in table 3. soft-start delay and ramp times it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer ma y wish to set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current management strategy or to control how fast a load ic is turned on. the zl2101 gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. table 3. zl2101 start-up sequence step # step name description time duration 1 power applied input voltage is applied to the zl2101?s vdd pins (vddp and vdds). depe nds on input supply ramp time 2 internal memory check the device will check fo r values stored in its internal memory. this step is also performed after a restore command. approximately 5ms to 10ms (device will ignore an enable signal or pmbus traffic during this period) 3 multi-mode pin check the device loads valu es configured by the multi-mode pins. 4 device ready the device is ready to accept an enable signal. - 5 pre-ramp delay the device requires approx imately 2ms following an enable signal and prior to ramping its output. additional pre-ramp delay may be configured using the ss pin. approximately 2ms table 4. resistors for setting output voltage r set (k ) v out (v) 10 0.6 11 0.7 12.1 0.75 13.3 0.8 14.7 0.9 16.2 1.0 17.8 1.1 19.6 1.2 21.5 1.25 23.7 1.3 26.1 1.4 28.7 1.5 31.6 1.6 34.8 1.7 38.3 1.8 42.2 1.9 46.4 2.0 51.1 2.1 56.2 2.2 61.9 2.3 68.1 2.4 75 2.5 82.5 2.6 90.9 2.7 100 2.8 110 2.9 121 3.0 133 3.1 147 3.2 162 3.3 178 5.0
zl2101 14 fn7730.0 january 23, 2012 the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay period is set using the ss pin. precise ramp delay timing mode reduces the delay time variations and is available when the appropriate bit in the misc_config register had been set. please refer to application note an2033 for details. the soft-start ramp timer enables a precisely controlled ramp to the nominal v out value that begins once the delay period has expired. the ramp-up is guaranteed monotonic and its slope may be precisely set using the ss pin. using the pin-strap method, the soft-start delay and ramp times can be set to one of three standard values according to table 5. if the desired soft-start delay and ramp times are not one of the values listed in table 5, the times can be set to a custom value by connecting a resistor from th e ss pin to sgnd using the appropriate resistor value from tabl e 6. the value of this resistor is measured upon start-up or restore and will not change if the resistor is varied after power has been applied to the zl2101 (see figure 15). the soft-start delay and ramp times can also be set to custom values via the i 2 c/smbus interface. when the ss delay time is set to 0ms, the device will begi n its ramp-up after the internal circuitry has initialized (~2ms). when the soft-start ramp period is set to 0ms, the output will ramp up as quickly as the output load capacitance and loop settings will allow. it is generally recommended to set the soft-start ramp to a value greater than 500s to prevent inadvertent fault conditions due to excessive inrush current. note that when auto compensation is enabled, the minimum t on_delay is 5ms. power-good (pg) the zl2101 provides a power-good (pg) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. by de fault, the pg pin will assert if the output is within +15%/-10% of the target voltage. these limits may be changed via the i 2 c/smbus interface. see application note an2033 for details. a pg delay period is the time from when all conditions for asserting pg are met and when the pg pin is actually asserted. this feature is commonly used instead of an external reset controller to signal the power supply is at its target voltage prior to enabling any powered circuitry. by default, the zl2101 pg delay is set to 1ms and may be changed using the i 2 c/smbus interface as described in an2033. table 5. soft-start delay and ramp settings ss pin setting delay and ramp time (ms) uvlo low 2 7.5v open 5 high 10 zl ss r ss figure 15. ss pin resistor connections table 6. delay and ramp configuration r ss (k ) delay time (ms) ramp time (ms) uvlo (v) 10 5 5 4.5 11 10 12.1 20 13.3 5 10 14.7 10 16.2 20 17.8 5 2 5.5 19.6 10 21.5 20 23.7 5 5 26.1 10 28.7 20 31.6 5 10 34.8 10 38.3 20 42.2 5 20 46.4 10 51.1 20 56.2 5 2 7.5 61.9 10 68.1 20 75 5 5 82.5 10 90.9 20 100 5 10 110 10 121 20 133 5 20 147 10 162 20
zl2101 15 fn7730.0 january 23, 2012 switching frequency and pll the zl2101 incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pll can be driven by an external clock source connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a clock source for other zilker labs devices. the sync pin is a unique pin that can perform multiple functions depending on how it is configured. the cfg pin is used to select the operating mode of the sync pin as shown in table 4. figure 16 illustrates the typical connections for each mode. configuration a: sync output when the sync pin is configured as an output (cfg pin is tied high), the device will run from its internal oscillator and will drive the resulting internal oscillator signal (preset to 400khz) onto the sync pin so other devices can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this mode. configuration b: sync input when the sync pin is configured as an input (cfg pin is tied low), the device will automatically check for an external clock signal on the sync pin each time the en pin is asserted. the internal oscillator will then synchr onize with the rising edge of the external clock. the incoming clock signal must be in the range of 200khz to 1mhz with a minimum duty cycle and must be stable when the en pin is asserted. the external clock signal must also exhibit the necessary performance requirements (see the ?electrical specifications? table beginning on page 6). in the event of a loss of the external clock signal, the output voltage may show transient over/undershoot. if this happens, the zl2101 will automatically switch to its internal oscillator and switch at a frequency close to the previous incoming frequency. configuration c: sync auto detect when the sync pin is configured in auto detect mode (cfg pin is left open), the device will automatically check for a clock signal on the sync pin after enable is asserted. if a valid clock signal is present, the zl2101?s oscillator will then synchronize with the rising edge of the external clock (refer to sync input description). if no incoming clock signal is present, the zl2101 will configure the switching frequency according to the state of the sync pin as listed in table 8. in this mode , the zl2101 will only read the sync pin connection du ring the start-up sequence. changes to the sync pin connection will not affect f sw until the power (vdds) is cycled off and on again. table 7. sync pin function selection cfg pin sync pin function low sync is configured as an input open auto detect mode high sync is configured as an output f sw = 400khz table 8. switching frequency selection sync pin frequency low 200khz open 400khz high 1mhz resistor see table 9 zl2106 logic high cfg sync 200 khz ? 1mhz zl2106 cfg sync 200 khz ? 1mhz zl2106 n/c cfg sync 200 khz ? 1m hz a) sync = output b) sync = input zl2106 n/c cfg sync zl2106 r syn c n/c cfg sync logic high logic low open c) sync = auto detect or or figure 16. sync pin configurations zl2101 zl2101 zl2101 zl2101 zl2101
zl2101 16 fn7730.0 january 23, 2012 if the user wishes to run the zl 2101 at a frequency not listed in table 8, the switching frequency can be set using an external resistor, r sync , connected between sync and sgnd using table 9. the switching frequency can also be set to any value between 200khz and 1mhz using the i 2 c/smbus interface. the available frequencies are defined by f sw = 8mhz/n, where whole number n is 8 n 40. see application note an2033 for details. if a value other than f sw = 8mhz/n is entered using a pmbus command, the internal circuitry will select the valid switching frequency value that is closest to the entered value. for example, if 810khz is entered, the device will select 800khz (n = 10). note: the switching frequency read back using the appropriate pmbus command will differ slightly from the selected value in table 9. the difference is due to hardware quantization. when multiple zilker labs devices are used together, connecting the sync pins together will force all devices to synchronize with each other. the cfg pin of one device must set its sync pin as an output and the remaining devices must have their sync pins set as an input or as auto detect. note: precise ramp timing mode must be disabled to use sync clock auto detect. component selection the zl2101 is a synchronous buck converter with integrated mosfets that uses an external inductor and capacitors to perform the power conversion process. the proper selection of the external components is crit ical for optimized performance. to select the appropriate external components for the desired performance goals, the power supply requirements listed in table 10 must be defined. design goal trade-offs the design of the buck power stage requires several compromises among size, efficiency and cost. the inductor core loss increases with frequency, so there is a trade-off between a small output filter made possible by a higher switching frequency and getting better power supply efficiency. size can be decreased by increasing the switching frequency at the expense of efficiency. cost can be minimized by using through-hole inductors and capacitors; however these components are physically large. to start the design, select a fr equency based on table 11. this frequency is a starting point and may be adjusted as the design progresses. inductor selection the output inductor selection process must include several trade- offs. a high inductance value will result in a low ripple current (i opp ), which will reduce output capacitance and produce a low output ripple voltage, but may al so compromise output transient load performance. therefore, a balance must be struck between output ripple and optimal load transient performance. a good starting point is to select the ou tput inductor ripple equal to the expected load transient step magnitude (i ostep ): table 9. r sync resistor values r sync (k ) f sw (khz) 10 200 11 222 12.1 242 13.3 267 14.7 296 16.2 320 17.8 364 19.6 400 21.5 421 23.7 471 26.1 533 28.7 571 31.6 615 34.8 667 38.3 727 42.2 889 46.4 1000 table 10. power supply requirements parameter range example value input voltage (v in )4.5v to 14.0v 12v output voltage (v out )0.6v to 5.0v 3.3v output current (i out ) 0a to 6a 4a output voltage ripple (v orip ) <3% of v out 1% of v out output load step (i ostep ) zl2101 17 fn7730.0 january 23, 2012 now the output inductance can be calculated using equation 3, where v inm is the maximum input voltage: the average inductor current is equal to the maximum output current. the peak inductor current (i lpk ) is calculated using equation 4 where i out is the maximum output current: select an inductor rated for the average dc current with a peak current rating above the peak current computed in equation 4. in overcurrent or short-circuit conditions, the inductor may have currents greater than 2x the normal maximum rated output current. it is desirable to use an inductor that still provides some inductance to protect the load and the internal mosfets from damaging currents in this situation. once an inductor is selected, the dcr and core losses in the inductor are calculated. use the dcr specified in the inductor manufacturer?s data sheet. i lrms is given by equation 6: where i out is the maximum output current. next, calculate the core loss of the selected induct or. since this calculation is specific to each inductor and manufacturer, refer to the chosen inductor data sheet. add the core loss and the dcr loss and compare the total loss to the maximum power dissipation recommendation in the inductor data sheet. output capacitor selection several trade-offs must also be considered when selecting an output capacitor. low esr values are needed to have a small output deviation during transient load steps (v osag ) and low output voltage ripple (v orip ). however, capacitors with low esr, such as semi-stable (x5r and x7r) dielectric ceramic capacitors, also have relatively low capacitance values. many designs can use a combination of high capacitance devices and low esr devices in parallel. for high ripple currents, a low capacitance value can cause a significant amount of output voltage ripple. likewise, in high transient load steps, a relatively large amount of capacitance is needed to minimize the output voltage deviation while the inductor current ramps up or down to the new steady state output current value. as a starting point, apportion one-half of the output ripple voltage to the capacitor esr and the other half to capacitance, as shown in equations 7 and 8: use these values to make an init ial capacitor selection, using a single capacitor or several capacitors in parallel. after a capacitor has been selected, the resulting output voltage ripple can be calculated using equation 9: because each part of this equation was made to be less than or equal to half of the allowed output ripple voltage, the v orip should be less than the desired maximum output ripple. input capacitor it is highly recommended that dedicated input capacitors be used in any point-of-load design, even when the supply is powered from a heavily filtered 5v or 12v ?bulk? supply from an off-line power supply. this is because of the high rms ripple current that is drawn by the buck converter topology. this ripple (i cinrms ) can be determined from equation 10: without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. the input capacitors should be rated at 1.2x the ripple current calculated in equation 10 to avoid overheating of the capacitors due to the high ripple current, which can cause premature failure. ceramic capacitors with x7r or x5r dielectric with low esr and 1.1x the maximum expected input voltage are recommended. bootstrap capacitor selection the high-side driver boost circuit utilizes an internal schottky diode (d b ) and an external bootstrap capacitor (c b ) to supply sufficient gate drive for the high-side mosfet driver. c b should be a 47nf ceramic type rated for at least 10v. c v2p5 selection this capacitor is used to both stabilize and provide noise filtering for the 2.5v internal power supply. it should be between 4.7f and 10f, should use a semi-stable x5r or x7r dielectric ceramic with a low esr (less than 10m ) and should have a rating of 4v or more. c vr selection this capacitor is used to both stabilize and provide noise filtering for the 7v reference supply. it should be between 4.7f and 10f, should use a semi-stable x5r or x7r dielectric ceramic capacitor with a low esr (less than 10m ) and should have a rating of 10v or more. because the current for the bootstrap supply is drawn from this capacitor, c vr should be sized at least 10x the value of c b so that a discharged c b does not cause the voltage on it to droop excessively during a c b recharge pulse. opp inm out out out i fsw v v v l ? ? ? ? ? ? ? ? ? = 1 (eq. 3) 2 opp out lpk i i i + = 2 lrms ldcr i dcr p = () 12 2 2 opp out lrms i i i + = 2 8 orip sw opp out v f i c = opp orip i v esr = 2 (eq. 8) out sw opp opp orip c f i esr i v + = 8 (eq. 9) ) 1 ( d d i i out cinrms ? =
zl2101 18 fn7730.0 january 23, 2012 c vra selection this capacitor is used to both st abilize and provide noise filtering for the analog 5v reference supply. it should be between 2.2f and 10f, should use a semi-s table x5r or x7 r dielectric ceramic capacitor with a low esr (less than 10m ) and should have a rating of 6.3v or more. thermal considerations in typical applications, the zl2101?s high efficiency will limit the internal power dissipation inside the package. however, in applications that require a high ambient operating temperature the user must perform some thermal analysis to ensure that the zl2101?s maximum junction temperature is not exceeded. the zl2101 has a maximum junction temperature limit of +125c, and the internal over-temperature limiting circuitry will force the device to shut down if its junction temperature exceeds this threshold. in order to calculate the maximum junction temperature, the user must first calculate the power dissipated inside the ic (p q ) as expressed in equation 11: the maximum operating junction temperature can then be calculated using equation 12: where t pcb is the expected maximum printed circuit board temperature and jc is the junction-to-case thermal resistance for the zl2101 package. current sensing and current limit threshold selection the zl2101 incorporates a patented ?lossless? current sensing method across the internal low-side mosfet that is independent of r ds(on) variations, including temperature. the default value for the gain, which does not represent a r ds(on) value, and the offset of the internal current sensing circuit can be modified by the iout_cal_gain and iout_cal_offset commands. the design should include a current limiting mechanism to protect the power supply from damage and prevent excessive current from being drawn from th e input supply in the event that the output is shorted to ground or an overload condition is imposed on the output. current limiting is accomplished by sensing the current through the circuit during a portion of the duty cycle. the current limit threshold is set to 9a by default. the current limit threshold can set to a custom value via the i 2 c/smbus interface. please refer to application note an2033 for further details. additionally, the zl2101 gives the power supply designer several choices for the fault response during over or under current conditions. the user can select the number of violations allowed before declaring a fault, a blanking time and the action taken when a fault is detected. the blanking ti me represents the time when no current measurement is taken. this is to avoid taking a reading just after a current load step (less accurate due to potential ringing). please refer to application no te an2033 for further details. loop compensation the zl2101 has an auto compensation feature that measures the characteristics of the power train and calculates the proper tap coefficients. auto compensation is configured using the fc pin as shown in table 12. () () () () () () () [] d r d r i p ql on ds qh on ds load q ? + = 1 2 (eq. 11) () jc q pcb j p t t max + = ? not stored single after auto comp 100% 11 k ? store in flash 12.1 k ? not stored repeat 1s 13.3 k ? store in flash 14.7 k ? not stored single after pg delay 16.2 k ? store in flash 17.8 k ? not stored repeat 1s 19.6 k ? store in flash 21.5 k ? store in flash single after auto comp 23.7 k ? not stored repeat 1min 26.1 k ? store in flash 28.7 k ? not stored single after pg delay 31.6 k ? store in flash 34.8 k ? not stored repeat 1min 38.3 k ? store in flash 42.2 k ? not stored single after auto comp 50% 46.4 k ? store in flash 51.1 k ? not stored repeat 1s 56.2 k ? store in flash 61.9 k ? not stored single after pg delay 68.1 k ? store in flash 75 k ? not stored repeat 1s 82.5 k ? store in flash 90.9 k ? not stored single after auto comp 100 k ? store in flash 110 k ? not stored repeat 1min 121 k ? store in flash 133 k ? not stored single after pg delay 147 k ? store in flash 162 k ? not stored repeat 1min 178 k ? store in flash
zl2101 19 fn7730.0 january 23, 2012 when auto compensation is enabled, the routine can be set to execute one time after ramp or periodically while regulating. note that the auto compensation feature requires a minimum t on_delay as described in "soft-start delay and ramp times" on page 14. if the device is configured to store auto comp values, the calculated compensation values will be saved in the auto comp store and may be read back through the pid_taps command. if repeat mode is enabled, the first auto comp results after the first ramp will be stored; the values calculated periodically are not stored in the auto comp store. when compensation values are saved in the auto comp store, the device will use those compensation values on subsequent regulation voltage. in repeat mode, the latest auto comp results will always be used during operation. stored auto co mp results can only be cleared by disabling auto comp store, which is not permitted while the output is enabled. however, sending the autocomp_control command while enabled in store mode will cause the next results to be stored, overwriting previously stored values. if auto compensation is disabled, the de vice will use the compensation parameters that are stored in the default_store or user_store. if the pg assert parameter is set to "use pg delay," pg will be asserted according to the power_good_delay command, after which auto comp will begin. when auto comp is enabled, the user must not program a po wer-good delay that will expire before the ramp is finished. if pg assert is set to "after auto comp," pg will be asserted immediately after the first auto comp cycle completes (power_good_delay will be ignored). the auto comp gain control scales the auto comp results to allow a trade-off between transi ent response and steady-state duty cycle jitter. a setting of 100% will provide the fastest transient response while a setting of 10% will produce the lowest jitter. note that if auto comp is enabled, for best results vin must be stable before auto comp begins, as shown in equation 13. the auto compensation function can also be configured via the auto_comp_config command and controlled using the auto_comp_control command over the i 2 c/smbus interface. please refer to application no te an2033 for further details. driver dead-time control the zl2101 utilizes a predetermined fixed dead-time applied between the gate drive signals for the top and bottom mosfets. in a synchronous buck converter, the mosfet drive circuitry must be operated such that the top and bottom mosfets are never in the conducting state at the same time. this is because potentially damaging currents flow in the circuit if both mosfets are on simultaneously for periods of time exceeding a few nanoseconds. conversely, long periods of time in which both mosfets are off reduces overall circuit efficiency by allowing current to flow in their parasitic body diodes. therefore, it is advantageous to minimize the dead-time to provide peak optimal efficiency without compromising system reliability. the zl2101 has op timized the dead-time for the integrated mosfets to maximizing efficiency. power management functional description input undervoltage lockout the input undervoltage lockout (u vlo) prevents the zl2101 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set to either 4.5v or 10.8v using the ss pin according to table 6. the uvlo voltage can also be set to any value between 2.85v and 16v via the i 2 c/smbus interface. once an input undervoltage fault condition occurs, the device can respond in a number of ways as follows: 1. continue operating without interruption. 2. continue operating for a given delay period, followed by shutdown if the fault still exists. the device will remain in shutdown until instructed to restart. 3. initiate an immediate shutdo wn until the fault has been cleared. the user can select a specific number of retry attempts. the default response from a uvlo fault is an immediate shutdown of the device. please refer to application note an2033 for details on how to configure the uvlo threshold or to select specific uvlo fault response options via the i 2 c/smbus interface. output overvoltage protection the zl2101 offers an internal output overvoltage protection circuit that can be used to prot ect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator is used to compare the actual output voltage (seen at the vsen pin) to a threshold set to 15% higher than the target output voltage (the default setting). if the vsen voltage exceeds this threshold, the pg pin will de-assert and the device can then respond in a number of ways as follows: 1. initiate an immediate shutdo wn until the fault has been cleared. the user can select a specific number of retry attempts. 2. turn off the high-side mosfet and turn on the low-side mosfet. the low-side mosfet remains on until the device attempts a restart. the default response from an over voltage fault is to immediately shut down. for continuous overvo ltage protection when operating from an external clock, the only allowed response is an immediate shutdown. please refer to application note an2033 for details on how to select spec ific overvoltage fault response options via i 2 c/smbus. output pre-bias protection an output pre-bias condition exists when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. certain applications require that the converter not be allowed to sink current during start up if a pre-bias condition exists at the output. the zl2101 provides pre- bias protection by sampling the output voltage prior to initiating an output ramp. vin vin nom -------------------- in% () 100% 1 256 vout ? vin nom ---------------------------- - + -------------------------------------- - (eq. 13)
zl2101 20 fn7730.0 january 23, 2012 if a pre-bias voltage lower than th e target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled. the output voltage is then ramped to the final regulation value at the ramp rate set by the ss pin. the actual time the output will take to ramp from the pre-bias voltage to the target voltage will vary depending on the pre-bias voltage but the total time elapse d from when the delay period expires and when the output reaches its target value will match the pre-configured ramp time (see figure 17). if a pre-bias voltage higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled with a pwm duty cycle that would ideally create the pre- bias voltage. once the pre-configured soft-start ramp period has expired, the pg pin will be asserted (assuming the pre-bias voltage is not higher than the overvoltage limit) . the pwm will then adjust its duty cycle to match the original target voltage and the output will ramp down to the pre-configured output voltage. if a pre-bias voltage higher than the overvoltage limit exists, the device will not initiate a turn-on sequence and will declare an overvoltage fault condition to exist. in this case, the device will respond based on the output over voltage fault response method that has been selected. see ?output overvoltage protection? on page 19 for response options due to an overvoltage condition. output overcurrent protection the zl2101 can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. once the current lim it threshold has been selected (see ?current sensing and current limit threshold selection? on page 18), the user may determine the desired course of action in response to the fault condition. the following overcurrent protection response options are available: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. 6. the default response from an overcurrent fault is an immediate shutdown of the device. please refer to application note an2033 for details on how to select specific overcurrent fault response options via i 2 c/smbus. thermal overload protection the zl2101 includes an on-chip thermal sensor that continuously measures the internal temperature of the die and will shutdown the device when the temperature exceeds the preset limit. the factory default temperature limit is set to +125c, but the user may set the limit to a different value if desired. see application note an2033 for details. note that setting a higher thermal limit via the i 2 c/smbus interface may result in permanent damage to the device. once the device has been disabled due to an internal temperature fault, the user may select one of several fault response options as follows: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. if the user has configured the devi ce to restart, the device will wait the preset delay period (if configured to do so) and will then check the device temperature. if the temperature has dropped below a threshold that is appr oximately +15c lower than the selected temperature fault limit, the device will attempt to re-start. if the temperature still exceeds the fault limit the device will wait the preset delay period and retry again. the default response from a temp erature fault is an immediate shutdown of the device. please refer to application note an2033 for details on how to select spec ific temperature fault response options via i 2 c/smbus. figure 17. output responses to pre-bias voltages
zl2101 21 fn7730.0 january 23, 2012 voltage tracking high performance systems place stringent demands on the order in which the power supply voltages turn on. this is particularly true when powering fpgas, asic s, and other advanced processor devices that require multiple supply voltages to power a single die. in most cases, the i/o interf ace operates at a higher voltage than the core and therefore th e core supply voltage must not exceed the i/o supply voltage according to the manufacturers' specifications. voltage tracking protects these sensitive ics by limiting the differential voltage among multiple power supplies during the power-up and power-down sequence. the zl2101 integrates a lossless tracking sche me that allows its output to track a voltage that is applied to the vtrk pin with no additional components required. figure 18 shows a basic i 2 c/smbus tracking configuration. please refer to application note an2033 for more information on configuring tracking mode using pmbus commands. figure 22 is an example of a basic pin-strap tracking configuration. the vtrk pin is an analog input that, when tracking mode is enabled, the voltage applied to the vtrk pin performs as a reference for the device's output voltage. the zl2101 offers two modes of tracking: coincident and ratiometric. figures 19 and 20 illustrate the output voltage waveform for the two tracking modes. 1. coincident. this mode config ures the zl2101 to ramp its output voltage at the same rate as the voltage applied to the vtrk pin. two options are available for this mode; a. track at 100% v out limited. member rail tracks the reference rail and stops when the member reaches its target voltage, figure 19 (a). b. track at 100% vtrk limited. member rail tracks the reference at the instantaneous voltage value applied to the vtrk pin, figure 19 (b). 2. ratiometric. this mode config ures the zl2101 to ramp its output voltage as a percentage of the voltage applied to the vtrk pin. the default setting is 50%, but an external resistor may be used to configure a different tracking ratio. a. track at 50% v out limited. member rail tracks the reference rail and stops when the member reaches 50% of the target voltage, figure 20 (a). b. track at 50% vtrk limited. member rail tracks the reference at the instantaneous voltage value applied to the vtrk pin until the member rail reaches 50% of the reference rail voltage, or if the member is configured to less than 50% of the reference the member will achieve its configured target, figure 20 (b). tracking overview when the zl2101 is configured to the voltage tracking mode, the voltage applied to the vtrk pin acts as a reference for the member device(s) output regula tion. the soft-start values (rise/fall times) are used to calculate the loop gain used during the turn-on/turn-off ramps, ther efore the minimum rise/fall time has been constrained to 5ms to ensure accuracy. tracking accuracy can be improved by increasing the rise and fall times beyond 5ms. tracking groups in a tracking group, the device configured to the highest voltage within the group is defined as the reference device. the device(s) that track the reference are called the member device(s). the reference device will control the ramp delay and ramp rate of all tracking devices and is not pl aced in the tracking mode. the reference device is configured to the highest output voltage for the group and all other device(s ) output voltages are meant to track and never exceed the reference device output voltage. the reference device must be configured to have a minimum time-on delay and time-on rise as shown in equation 14. this delay allows the member device(s) to prepare their control loops for tracking followin g the assertion of enable. the member device time-off delay has been redefined to describe the time that the vtrk pin will follow the reference voltage after enable is de-asserted. the delay setting sets the figure 19. coincident tracking figure 18. basic i 2 c tracking configuration zl2101 vtrk sw sda scl l3 vout_m member zl2101 sw scl sda l4 vout_r reference sda scl track @ 100% v out limited v ref > v mem en 0 en 0 ~ ~ ~ ~ t on_dly t off_dly v ref v mem track @ 100% v trk limited v ref = v mem ~ ~ t on_dly t off_dly v ref v mem v ref = 1.8v v mem = 0.9v a. b. v ref = 1.8v v mem = 1.8v figure 20. ratiometric tracking en 0 en 0 ~ ~ ~ ~ ~ ~ ~ ~ a. b. track @ 50% v out limited track @ 50% v trk limited v ref = 1.8v v mem = 0.9v v ref = 1.8v v mem = 0.9v t on_dly t off_dly v ref = 1.8v v mem = 0.9v v ref = 1.8v v mem = 0.9v t on_dly t off_dly v mem v mem v ref v ref (eq. 14) ton dly(ref) ton dly(mem) + ton rise(ref) + 5ms ton dly(mem) + 10ms
zl2101 22 fn7730.0 january 23, 2012 timeout for the member's output voltage to turnoff in the event that the reference output voltag e does not achieve zero volts. the member device(s) must have a minimum time-off delay of as shown in equation 15. it is assumed for a tracking group, that all of the enable pins are connected together and driven by a single logic so urce or pmbus broadcast enable is used. the configuration settings fo r figures 19 and 20 are shown below in figure 21. in each case the reference and member rise times are set to the same value. tracking configured by pin-strap tracking is enabled with the cfg pin as shown in table 16 on page 24, and configured to a specific ramp rate using the ss pin, as shown in table 13 on page 23. figure 22 shows the basic schematic of pin-strap tracking. voltage margining the zl2101 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. the mgn command is set by driving the mgn pin or through the i 2 c/smbus interface. the mgn pin is a tri-level input that is continuous ly monitored and can be driven directly by a processor i/o pin or other logic-level output. the zl2101?s output will be forced higher than its nominal set point when the mgn command is set high, and the output will be forced lower than its nominal set point when the mgn command is set low. default margin limits of v nom 5% are pre-loaded in the factory, but the margin limits can be modified through the i 2 c/smbus interface to as high as v nom + 10% or as low as 0v, where v nom is the nominal output voltage set point determined by the vset pin. a safety feature prevents the user from configuring the output voltage to exceed v nom + 10% under any conditions. the margin limits and the mg n command can both be set individually through the i 2 c/smbus interface. additionally, the transition rate between the nomi nal output voltage and either margin limit can be configured through the i 2 c/smbus interface. please refer to application note an2033 for detailed instructions on modifying the marg ining configurations. (eq. 15) toff dly(mem) toff dly(ref) + toff fall(ref) + 5ms rail vout set (volts) time ? on ? dly (ms) time ? on rise (ms) time ? off ? dly (ms) time ? off fall ( ? ms) mode reference 1.8 15 5 5 5 track ? disabled member 0.9 5 5 15 5 100% ? vout ? limited rail vout ? set (volts) time ? on ? dly (ms) time ? on rise (ms) time ? off ? dly (ms) time ? off fall ( ? ms) mode reference 1.8 15 5 5 5 track ? disabled member 1.8 5 5 15 5 100% ? vtrk ? limited rail vout ? set (volts) time ? on ? dly (ms) time ? on rise (ms) time ? off ? dly (ms) time ? off fall ( ? ms) mode reference 1.8 15 5 5 5 track ? disabled member 0.9 5 5 15 5 track ? 50% ? vout ? limited rail vout ? set (volts) time ? on ? dly (ms) time ? on rise (ms) time ? off ? dly (ms) time ? off fall ( ? ms) mode reference 1.8 15 5 5 5 track ? disabled member 1.8 5 5 15 5 track ? 50% ? vtrk ? limited tracking ? configuration ? figure ? 20 ? (a) tracking ? configuration ? figure ? 20 ? (b) tracking ? configuration ? figure ? 21 ? (a) tracking ? configuration ? figure ? 21 ? (b) figure 21. tracking configuration for figures 19 and 20 0.8 figure 22. basic pin-strap tracking configuration zl2101 sw en l2 vout_m member zl2101 sw en l1 vout_r reference enable r1 r3 r2 r4 vtrk cfg ss cfg ss
zl2101 23 fn7730.0 january 23, 2012 i 2 c/smbus communications the zl2101 provides an i 2 c/smbus digital interface that enables the user to configure all aspects of the device operation as well as monitor the input and output parameters. the zl2101 can be used with any standard 2-wire i 2 c host device. in addition, the device is compatible with smbus version 2.0 and includes an salrt line to help mitigate bandwidth limitations related to continuous fault mo nitoring. pull-up resistors are required on the i 2 c/smbus as specified in the smbus 2.0 specification. the zl2101 accepts most standard pmbus commands. when controlling the device with pmbus commands, it is recommended that the enable pin is tied to sgnd. i 2 c/smbus device address selection when communicating with mu ltiple devices using the i 2 c/smbus interface, each device must have its own unique address so the host can distinguish between the devices. the device address can be set according to the pin-strap options listed in table 14. address values are right-justified. if additional device addresses are required, a resistor can be connected to the sa pin according to table 15 to provide up to 30 unique device addresses. digital-dc bus the digital-dc communications (ddc) bus is used to communicate between zilker labs digital-dc devices. this dedicated bus provides the communication channel between devices for features such as sequencing and fault spreading. the ddc pin on all digital-dc device s in an application should be connected together. a pull-up resistor is required on the ddc bus in order to guarantee the rise ti me as expressed in equation 16: where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to vra or to an external 3.3v or 5v supply as long as this voltage is present prior to or during device power-up. as rules of thumb, each device connected to the ddc bus presents approximately 10pf of capacitive loading, and each inch of fr4 pcb trace introduces approximately 2pf. the ideal design will use a central pull-up resistor that is well matched to the total load capacitance. in power module applications, the user should consider whether to place the pull-up resistor on the module or on the pcb of the end application. the minimum pull-up resistance should be limited to a value that enables any device to assert the bu s to a voltage that will ensure a logic 0 (typically 0.8v at the de vice monitoring point) given the pull-up voltage (5v if tied to vra) and the pull-down current capability of the zl2101 (nominally 4ma). table 13. tracking mode configuration r ss (k ) uvlo (v) tracking ratio (%) upper track limit ramp-up/down behavior 19.6 5.5 100 limited by target voltage output not allowed to decrease before pg 21.5 output will always follow vtrk 23.7 limited by vtrk pin voltage output not allowed to decrease before pg 26.1 output will always follow vtrk 28.7 50 limited by target voltage output not allowed to decrease before pg 31.6 output will always follow vtrk 34.8 limited by vtrk pin voltage output not allowed to decrease before pg 38.3 output will always follow vtrk 56.2 7.5 100 limited by target voltage output not allowed to decrease before pg 61.9 output will always follow vtrk 68.1 limited by vtrk pin voltage output not allowed to decrease before pg 75 output will always follow vtrk 82.5 50 limited by target voltage output not allowed to decrease before pg 90.9 output will always follow vtrk 100 limited by vtrk pin voltage output not allowed to decrease before pg 110 output will always follow vtrk table 14. smbus device address selection sa pin setting smbus address low 0x20 open 0x21 high 0x22 (eq. 16) rise time = r pu ?c load 1s
zl2101 24 fn7730.0 january 23, 2012 phase spreading when multiple point of load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the i rms 2 are reduced dramatically. in order to enable phase spreading, all converters must be synchronized to the same switchin g clock. the cfg pin is used to set the configuration of the sync pin for each device as described in ?switching frequency and pll? on page 15. selecting the phase offset for the device is accomplished by selecting a device address according to the following equation: phase offset = device address x 45 for example: ? a device address of 0x00 or 0x20 would configure no phase offset ? a device address of 0x01 or 0x21 would configure 45 of phase offset ? a device address of 0x02 or 0x22 would configure 90 of phase offset the phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments via the i 2 c/smbus interface. refer to application note an2033 for further details. output sequencing a group of zilker labs devices may be configured to power up in a predetermined sequence. this feature is especially useful when powering advanced processors, fpgas, and asics that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up from occurring. multi-device sequencing can be achieved by configuring each device through the i 2 c/smbus interface or by using zilker labs patented autonomous sequencing mode. autonomous sequencing mode configures sequencing by using events transmitted between devices over the ddc bus. the sequencing order is determined using each device?s smbus address. using autonomous sequ encing mode (configured using the cfg pin), the devices must be assigned sequential smbus addresses with no missing addresse s in the chain. this mode will also constrain each device to have a phase offset according to its smbus address as described in section ?phase spreading? on page 24. table 15. smbus address values r sa (k )smbus address 10 0x20 11 0x21 12.1 0x22 13.3 0x23 14.7 0x24 16.2 0x25 17.8 0x26 19.6 0x27 21.5 0x28 23.7 0x29 26.1 0x2a 28.7 0x2b 31.6 0x2c 34.8 0x2d 38.3 0x2e 42.2 0x2f 46.4 0x30 51.1 0x31 56.2 0x32 61.9 0x33 68.1 0x34 75 0x35 82.5 0x36 90.9 0x37 100 0x38 110 0x39 121 0x3a 133 0x3b 147 0x3c 162 0x3d table 16. cfg pin configurations for sequencing and tracking r cfg sync pin configuration sequencing configuration low input sequencing and tracking are disabled. open auto detect high output 10k input sequencing and tracking are disabled. 11k auto detect 12.1k output 14.7k input device is first in nested sequence. tracking disabled. 16.2k auto detect 17.8k output 21.5k input device is last in nested sequence. tracking disabled. 23.7k auto detect 26.1k output
zl2101 25 fn7730.0 january 23, 2012 the sequencing group will turn on in order starting with the device with the lowest smbus ad dress and will continue through to turn on each device in the address chain until all devices connected have been turned on. when turning off, the device with the highest smbus address will turn off first followed in reverse order by the other devices in the group. sequencing is configured by conn ecting a resistor from the cfg pin to ground as described in table 16. the cfg pin is also used to set the configuration of the sync pin as well as to determine the sequencing method and order. please refer to section ?switching frequency and pll? on page 15 for more details on the operating parameters of the sync pin. multiple device sequencing may also be achieved by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the de vice that will follow in the sequencing chain. this method pl aces fewer restrictions on the smbus address (no need of sequen tial address) and also allows the user to assign any phase offset to any device irrespective of its smbus device address. the enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven lo w to initiate a sequenced turnoff of the group. please refer to application note an2033 for details on sequencing via the i 2 c/smbus interface. fault spreading digital-dc devices can be config ured to broadcast a fault event over the ddc bus to the other devices in the group. when a non- destructive fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the ddc bus. the other devices on the ddc bus will shut down together if configured to do so, and will attempt to re- start in their prescribed orde r if configured to do so. monitoring via i 2 c/smbus a system controller can monitor a wide variety of different zl2101 system parameters through the i 2 c/smbus interface. the device can monitor for fault conditions by monitoring the salrt pin, which will be pulled low when any number of pre- configured fault conditions occur. the device can also be monitored continuously for any number of power conversion parameters including input voltage, output voltage, output current, internal junction temperature, switching frequency and duty cycle. the pmbus host should respond to salrt as follows: 1. zl device pulls salrt low. 2. pmbus host detects that salrt is now low, performs transmission with alert respon se address to find which zl device is pulling salrt low. 3. pmbus host talks to the zl de vice that has pulled salrt low. the actions that the host performs are up to the system designer. if multiple devices are faulting, salrt will still be low after doing the above steps and will require transmission with the alert response address repeatedly until all faults are cleared. please refer to application note an2033 for details on how to monitor specific parameters via the i 2 c/smbus interface. snapshot? parametric capture the zl2101 offers a special feat ure that enables the user to capture parametric data during normal operation or following a fault. the snapshot functionality is enabled by setting bit 1 of misc_config to 1. see an2033 for details on using snapshot in addition to the parameters supported. the snapshot feature enables the user to read the parameters via a bloc k read transfer through the smbus. this can be done during normal operation, although it should be noted that reading th e 22 bytes will occupy the smbus for some time. the snapshot_control command enables the user to store the snapshot parameters to fl ash memory in response to a pending fault as well as to read the stored data from flash memory after a fault has occurred. table 17 describes the usage of this command. automatic writes to flash memory following a faul t are triggered when any fault threshold level is exceeded, provided that the specific fault?s response is to shut down (writing to flash memory is not allowed if the device is configured to re-try following the specific fault condition). it should also be noted that the device?s v dd voltage must be maintained during the time when the device is writing the data to flash memory; a process that requires between 700s to 1400s depending on whether th e data is set up for a block write. undesirable results may be observed if the device?s v dd supply drops below 3.0v during this process. in the event that the device experiences a fault and power is lost, the user can extract the last snapshot parameters stored during the fault by writing a 1 to snapshot_control (transfers data from flash memory to ram) and then issuing a snapshot command (reads data from ram via smbus). 31.6k input device is middle in nested sequence. tracking disabled. 34.8k auto detect 38.3k output 46.4k input sequence disabled. tracking enabled as defined in table 13. 51.1k auto detect 56.2k output table 16. cfg pin configurations for sequencing and tracking (continued) r cfg sync pin configuration sequencing configuration table 17. snapshot_control command data value description 1 copies current snapshot values from flash memory to ram for immediate access using snapshot command. 2 writes current snapshot values to flash memory. only available when device is disabled.
zl2101 26 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7730.0 january 23, 2012 for additional products, see www.intersil.com/product_tree non-volatile memory and device security features the zl2101 has internal non-volatile memory where user configurations are stored. integr ated security measures ensure that the user can only restore the device to a level that has been made available to them. refer to ?start-up procedure? on page 13 for details on how the device loads stored values from internal memory during start-up. during the initialization process, the zl2101 checks for stored values contained in its internal memory. the zl2101 offers two internal memory storage units that are accessible by the user as follows: 1. default store : a power supply module manufacturer may want to protect the module from damage by preventing the user from being able to modify certain values that are related to the physical construction of the module. in this case, the module manufacturer would use the default store and would allow the user to restore the de vice to its default setting but would restrict the user from restoring the device to the factory settings. 2. user store : the manufacturer of a piece of equipment may want to provide the ability to modify certain power supply settings while still protecting the equipment from modifying values that can lead to a system level fault. the equipment manufacturer would use the user store to achieve this goal. please refer to application note an2033 for details on how to set specific security measures via the i 2 c/smbus interface. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: zl2101 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change january 23, 2012 fn7730.0 initial release
zl2101 27 fn7730.0 january 23, 2012 package outline drawing l36.6x6c 36 lead quad flat no-lead plastic package rev 0, 4/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view jedec reference drawing: mo-220vjjd. 7. ( 4. 10 ) ( 5. 60 typ ) (36x 0.25 ) ( 36x 0.80 ) ( 36 x 0 . 50 ) 0 . 00 min. 0 . 05 max. 0 . 2 ref c max 1.00 5 0.10 c 0.08 c c 6.00 (4x) 0.15 6 pin 1 index area 6.00 b a see detail "x" 4 .10 0.10 36x 0.60 0.10 36x 0.25 c 0.10 m a b 4 19 18 9 10 pin #1 27 28 36x 1 36 0.50 6 4.0 4x index area

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